- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369760 > LH28F800BGHB-TTL90 x16 Flash EEPROM PDF資料下載
參數(shù)資料
| 型號： | LH28F800BGHB-TTL90 |
| 英文描述： | x16 Flash EEPROM |
| 中文描述： | x16閃存EEPROM |
| 文件頁數(shù)： | 46/56頁 |
| 文件大小： | 373K |
| 代理商： | LH28F800BGHB-TTL90 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
SYMBOL
t
AVAV
PARAMETER
NOTE
MIN.
70
MAX.
MIN.
80
MAX.
MIN.
100
MAX.
Write Cycle Time
RP# High Recovery to CE#
Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
WP# V
IH
Setup to CE# Going High
V
PP
Setup to CE# Going High
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to STS Going Low
Write Recovery before Read
V
PP
Hold from Valid SRD,
STS High Z
WP# V
IH
Hold from Valid SRD,
STS High Z
NOTES :
1.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold
and inactive WE# times should be measured relative to
the CE# waveform.
2.
Sampled, not 100% tested.
3.
Refer to
Table 3
for valid A
IN
and D
IN
for block erase,
full chip erase, (multi) word/byte write or block lock-bit
configuration.
4.
V
PP
should be held at V
PPH1
until determination of block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
ns
t
PHEL
2
1
1
1
μs
t
WLEL
t
ELEH
t
SHEH
t
VPEH
t
AVEH
t
DVEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHRL
t
EHGL
0
50
100
100
40
40
5
5
0
25
0
50
100
100
40
40
5
5
0
25
0
50
100
100
40
40
5
5
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
3
3
90
90
90
0
0
0
t
QVVL
2, 4
0
0
0
ns
t
QVSL
2, 4
0
0
0
ns
LH28F160S5-L/S5H-L
- 46 -
VERSIONS
V
CC
±0.25 V
V
CC
±0.5 V
(NOTE 5)
LH28F160S5-L70
(NOTE 6)
LH28F160S5-L10
(NOTE 6)
LH28F160S5-L70
UNIT
V
CC
= 5.0±0.25 V, 5.0±0.5 V, T
A
= 0 to +70°C
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
(NOTE 1)
[LH28F160S5-L]
5.
See
Fig. 12
"
Transient Input/Output Reference
Waveform
" and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
" (High Speed Configuration) for testing
characteristics.
See
Fig. 13
"
Transient Input/Output Reference
Waveform
" and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
" (Standard Configuration) for testing
characteristics.
6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH28F800BGN-BL12 | x16 Flash EEPROM |
| LH28F800BGN-BL85 | x16 Flash EEPROM |
| LH28F800BGN-TL12 | x16 Flash EEPROM |
| LH28F800BGN-TL85 | x16 Flash EEPROM |
| LH28F800BVHE-BV85 | x8/x16 Flash EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F800BGHEBL12 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGHE-BL12 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGHEBL85 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGHE-BL85 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGHETL12 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。