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參數(shù)資料
| 型號： | LH28F640BFHB-PBTL60 |
| 英文描述： | Flash ROM |
| 中文描述： | 閃存ROM |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LH28F640BFHB-PBTL60 |
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LH28F160S5-L/S5H-L
- 14 -
sequence) may be performed. The status register
may be polled to determine if an error occurs
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
PP
voltage. RP#
must be V
IH
. This command is not functional during
block erase, full chip erase, (multi) word/byte write,
block lock-bit configuration, block erase suspend or
(multi) word/byte write suspend modes.
4.5
Query database can be read by writing Query
command (98H). Following the command write,
read cycle from address shown in
Table 6 through
Table 10
retrieve the critical information to write,
erase and otherwise control the flash component.
A
0
of query offset address is ignored when x8
mode (BYTE# = V
IL
).
Query Command
Query data are always presented on the low-byte
data output (DQ
0
-DQ
7
). In x16 mode, high-byte
(DQ
8
-DQ
15
) outputs 00H. The bytes not assigned
to any information or reserved for future use are set
to "0". This command functions independently of
the V
PP
voltage. RP# must be V
IH
.
Table 5 Example of Query Structure Output
4.5.1 BLOCK STATUS REGISTER
This field provides lock configuration and erase
status for the specified block. These informations
are only available when device is ready (SR.7 = 1).
If block erase or full chip erase operation is finished
irregularly, block erase status bit will be set to "1". If
bit 1 is "1", this block is invalid.
MODE
OFFSET ADDRESS
OUTPUT
DQ
15-8
DQ
7-0
A
5
, A
4
, A
3
, A
2
, A
1
, A
0
1, 0, 0, 0, 0, 0 (20H)
1, 0, 0, 0, 0, 1 (21H)
1, 0, 0, 0, 1, 0 (22H)
1, 0, 0, 0, 1, 1 (23H)
A
5
, A
4
, A
3
, A
2
, A
1
1, 0, 0, 0, 0 (10H)
1, 0, 0, 0, 1 (11H)
High Z
High Z
High Z
High Z
"Q"
"Q"
"R"
"R"
x8 mode
x16 mode
00H
00H
"Q"
"R"
Table 6 Query Block Status Register
OFFSET
(Word Address)
(BA+2)H
LENGTH
DESCRIPTION
01H
Block Status Register
bit0
Block Lock Configuration
0 = Block is unlocked
1 = Block is locked
bit1
Block Erase Status
0 = Last erase operation completed successfully
1 = Last erase operation not completed successfully
bit2-7 Reserved for future use
NOTE :
BA = The beginning of a Block Address.
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PDF描述 |
|---|---|
| LH28F640BFHB-PTTL60 | Flash ROM |
| LH28F800BGHB-TTL90 | x16 Flash EEPROM |
| LH28F800BGN-BL12 | x16 Flash EEPROM |
| LH28F800BGN-BL85 | x16 Flash EEPROM |
| LH28F800BGN-TL12 | x16 Flash EEPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F640BFHB-PTTL60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F640BFHE-PBTL60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F640BFHE-PBTL70A | 功能描述:閃存 64Mb (x16)3V OTP Dual Supply RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| LH28F640BFHE-PBTL80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F640BFHE-PBTL90 | 制造商:Sharp Microelectronics 功能描述:NOR Flash Parallel 3V 64Mbit 4M x 16bit 90ns 48-Pin TSOP 制造商:Sharp Microelectronics Corporation 功能描述:NOR Flash Parallel 3V 64Mbit 4M x 16bit 90ns 48-Pin TSOP |
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