參數(shù)資料
型號： LH28F400SUN-NC80
廠商： Sharp Corporation
英文描述： 4M (512K 】 8, 256K 】 16) Flash Memory
中文描述： 4分（為512k】8，256K】16）快閃記憶體
文件頁數(shù)： 20/35頁
文件大小： 294K
代理商： LH28F400SUN-NC80
LH28F400SU-NC
4M (512K × 8, 256K × 16) Flash Memory
20
Timing Nomenclature
For 5.0 V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
t
CE
t
OE
t
ACC
t
AVQV
t
AS
t
DH
t
ELQV
t
GLQV
time (t) from CE
(E) going low (L) to the outputs (Q) becoming valid (V)
time (t) from OE
(G) going low (L) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
t
AVWH
t
WHDX
time (t) from address (A) valid (V) to WE
(W) going high (H)
time (t) from WE
(W) going high (H) to when the data (D) can become undefined (X)
Figure 15. Transient Input/Output
Reference Waveform (V
CC
= 5.0 V ±0.5 V)
Figure 17. Transient Equivalent Testing
Load Circuit (V
CC
= 5.0 V ±0.5 V)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE
(Chip Enable)
X
Driven, but not necessarily valid
G
OE
(Output Enable)
Z
High Impedance
W
WE (Write Enable)
P
RP
(Deep Power-Down Pin)
R
RY
/BY
(Ready/Busy)
V
Any Voltage Level
5 V
V
CC
at 4.5 V Min.
INPUT
TEST POINTS
OUTPUT
2.4
0.45
2.0
0.8
2.0
0.8
28F400SUT-NC60-13
NOTE:
AC test inputs are driven at V
OH
(2.4 V
TTL
) for a Logic '1' and V
OL
(0.45 V
TTL
) for a Logic '0'. Input timing begins at V
IH
(2.0 V
TTL
)
and V
IL
(0.8 V
TTL
). Output timing ends at V
IH
and V
IL
. Input rise
and fall times (10% to 90%) < 10 ns.
Figure 16. Transient Input/Output
Reference Waveform (V
CC
= 5.0 V ±.25 V)
2.5 ns OF 25
TRANSMISSION LINE
TOTAL CAPACITANCE = 100 pF
FROM OUTPUT
UNDER TEST
TEST
POINT
28F400SUT-NC60-15
Figure 18. Transient Equivalent Testing
Load Circuit (V
CC
= 5.0 V ±.25 V)
2.5 ns OF 83
TRANSMISSION LINE
TOTAL CAPACITANCE = 30 pF
FROM OUTPUT
UNDER TEST
TEST
POINT
28F400SUT-NC60-16
INPUT
0.0
TEST POINTS
OUTPUT
3.0
1.5
1.5
28F400SUT-NC60-14
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins,
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 10 ns.
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