參數(shù)資料
型號(hào)： LH28F400BGHB-TL12
英文描述： x16 Flash EEPROM
中文描述： x16閃存EEPROM
文件頁(yè)數(shù)： 11/56頁(yè)
文件大?。?/td> 373K
代理商： LH28F400BGHB-TL12
- 11 -
LH28F160S5-L/S5H-L
Table 2.1 Bus Operations (BYTE# = V
IH
)
RP#
CE
0
#
CE
1
#
V
IH
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
X
X
MODE
NOTE
1, 2, 3, 9
3
OE#
V
IL
V
IH
WE#
V
IH
V
IH
ADDRESS
X
X
V
PP
X
X
DQ
0-15
D
OUT
High Z
STS
X
X
Read
Output Disable
Standby
3
X
X
X
X
High Z
X
Deep Power-Down
Read Identifier
Codes
4
X
X
X
X
High Z
High Z
9
V
IH
V
IL
V
IL
V
IL
V
IH
See
Fig. 2
See
Table
6 through 10
X
X
(
NOTE 5)
High Z
Query
9
V
IH
V
IL
V
IL
V
IL
V
IH
X
(
NOTE 6)
High Z
Write
3, 7, 8, 9
V
IH
V
IL
V
IL
V
IH
V
IL
X
D
IN
X
Table 2.2 Bus Operations (BYTE# = V
IL
)
RP#
CE
0
#
CE
1
#
V
IH
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
X
X
MODE
NOTE
1, 2, 3, 9
3
OE#
V
IL
V
IH
WE#
V
IH
V
IH
ADDRESS
X
X
V
PP
X
X
DQ
0-7
D
OUT
High Z
STS
X
X
Read
Output Disable
Standby
3
X
X
X
X
High Z
X
Deep Power-Down
Read Identifier
Codes
4
X
X
X
X
High Z
High Z
9
V
IH
V
IL
V
IL
V
IL
V
IH
See
Fig. 2
See
Table
6 through 10
X
X
(NOTE 5)
High Z
Query
9
V
IH
V
IL
V
IL
V
IL
V
IH
X
(NOTE 6)
High Z
Write
NOTES :
1.
Refer to
Section 6.2.3
"
DC CHARACTERISTICS
"
.
When V
PP
≤
V
PPLK
, memory contents can be read, but
not altered.
2.
X can be V
IL
or V
IH
for control pins and addresses, and
V
PPLK
or V
PPH1
for V
PP
. See
Section 6.2.3
"
DC
CHARACTERISTICS
"
for V
PPLK
and V
PPH1
voltages.
3.
STS is V
OL
(if configured to RY/BY# mode) when the
WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
3, 7, 8, 9
V
IH
V
IL
V
IL
V
IH
V
IL
X
D
IN
X
4.
RP# at GND±0.2 V ensures the lowest deep power-
down current.
See
Section 4.2
for read identifier code data.
See
Section 4.5
for query data.
Command writes involving block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when V
PP =
V
PPH1
and V
CC =
V
CC1/2
.
Refer to
Table 3
for valid D
IN
during a write operation.
Don’t use the timing both OE# and WE# are V
IL
.
5.
6.
7.
8.
9.
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