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參數資料
| 型號： | LH28F160S3HR-L10 |
| 英文描述： | x8/x16 Flash EEPROM |
| 中文描述： | x8/x16閃存EEPROM |
| 文件頁數： | 18/56頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LH28F160S3HR-L10 |
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4.6
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by a block erase
confirm. This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence
is written, the device automatically outputs status
register data when read (see
Fig. 3
). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit
SR.7.
Block Erase Command
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V
CC =
V
CC1/2
and V
PP
= V
PPH1
. In the absence of this
high voltage, block contents are protected against
erasure. If block erase is attempted while V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to "1". Successful
block erase requires that the corresponding block
lock-bit be cleared or if set, that WP# = V
IH
. If block
erase is attempted when the corresponding block
lock-bit is set and WP# = V
IL
, SR.1 and SR.5 will
be set to "1".
4.7
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A full chip
erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0
to block 31 block by block. This command
sequence requires appropriate sequencing. Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle full chip erase sequence is
written, the device automatically outputs status
register data when read (see
Fig. 4
). The CPU can
detect full chip erase completion by analyzing the
output data of the STS pin or status register bit
SR.7.
Full Chip Erase Command
When the full chip erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued. If error is detected on a
block during full chip erase operation, WSM stops
erasing. Reading the block valid status by issuing
Read ID Codes command or Query command
informs which blocks failed to its erase.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Full Chip
Erase command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable full chip erasure can only occur when V
CC =
V
CC1/2
and V
PP =
V
PPH1
. In the absence of this high
voltage, block contents are protected against
erasure. If full chip erase is attempted while V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to "1". When
WP# = V
IH
, all blocks are erased independent of
block lock-bits status. When WP# = V
IL
, only
unlocked blocks are erased. In this case, SR.1 and
SR.4 will not be set to "1". Full chip erase can not
be suspended.
LH28F160S5-L/S5H-L
相關PDF資料 |
PDF描述 |
|---|---|
| LH28F160S3HR-L13 | EEPROM|FLASH|1MX16/2MX8|CMOS|TSSOP|56PIN|PLASTIC |
| LH28F160S3HT-L10 | x8/x16 Flash EEPROM |
| LH28F160S3HT-L13 | EEPROM|FLASH|1MX16/2MX8|CMOS|TSSOP|56PIN|PLASTIC |
| LH28F160S3NS-L13 | EEPROM|FLASH|1MX16/2MX8|CMOS|SOP|56PIN|PLASTIC |
| LH28F160S3R-L10 | x8/x16 Flash EEPROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LH28F160S3HR-L13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|1MX16/2MX8|CMOS|TSSOP|56PIN|PLASTIC |
| LH28F160S3HT-L10 | 制造商:Sharp Microelectronics Corporation 功能描述:NOR Flash Parallel 3V 16Mbit 2M/1M x 8bit/16bit 100ns 56-Pin TSOP |
| LH28F160S3HT-L10A | 功能描述:IC FLASH 16MBIT 100NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| LH28F160S3HT-L13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|1MX16/2MX8|CMOS|TSSOP|56PIN|PLASTIC |
| LH28F160S3HT-L75A | 制造商:Sharp Microelectronics Corporation 功能描述: |
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