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參數(shù)資料
| 型號(hào)： | LH28F004SU-Z9 |
| 廠商： | Sharp Corporation |
| 英文描述： | 4M (512 】 8) Flash Memory |
| 中文描述： | 4分（512】8）閃存 |
| 文件頁(yè)數(shù)： | 27/31頁(yè) |
| 文件大小： | 249K |
| 代理商： | LH28F004SU-Z9 |
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4M (512K × 8) Flash Memory
LH28F004SU-LC
27
AC Characteristics for CE
- Controlled Command Write Operations
1
V
CC
= 3.3 V ± 0.3 V, T
A
= 0°C to +70°C
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE
for all Command Write operations.
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
t
AVAV
Write Cycle Time
120
ns
t
PHWL
RP
Setup to WE Going Low
480
ns
3
t
VPEH
V
PP
Setup to CE
Going High
100
ns
3
t
WLEL
WE Setup to CE
Going Low
0
ns
t
AVEH
Address Setup to CE
Going High
110
ns
2, 6
t
DVEH
Data Setup to CE
Going High
110
ns
2, 6
t
ELEH
CE
Pulse Width
110
ns
t
EHDX
Data Hold from CE
High
5
ns
2
t
EHAX
Address Hold from CE
High
5
ns
2
t
EHWH
WE Hold from CE
High
5
ns
t
EHEL
CE
Pulse Width High
60
ns
t
GHEL
Read Recovery before Write
0
ns
t
EHRL
CE
High to RY
/BY
Going Low
100
ns
t
RHPL
RP
Hold from Valid Status Register
Data and RY
/BY
High
0
ns
3
t
PHEL
RP
High Recovery to CE
Going Low
1
μs
t
EHGL
Write Recovery before Read
95
ns
t
QVVL
V
PP
Hold from Valid Status Register
Data and RY
/BY
High
0
μs
t
EHQV1
t
EHQV2
Duration of Byte Write Operation
20
8
μs
4, 5
Duration of Block Erase Operation
0.3
s
4
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