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參數(shù)資料
| 型號： | LH28F004SCT-L12 |
| 英文描述： | x8 Flash EEPROM |
| 中文描述： | x8閃存EEPROM的 |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LH28F004SCT-L12 |
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- 22 -
LH28F160S5-L/S5H-L
protected against alteration. A successful clear
block lock-bits operation requires WP# = V
IH
. If it is
attempted with WP# = V
IL
, SR.1 and SR.5 will be
set to "1" and the operation will fail. Clear block
lock-bits operation with V
IH
< RP# produce spurious
results and should not be attempted.
If a clear block lock-bits operation is aborted due to
V
PP
or V
CC
transition out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
4.14 STS Configuration Command
The Status (STS) pin can be configured to different
states using the STS Configuration command.
Once the STS pin has been configured, it remains
in that configuration until another configuration
command is issued, the device is powered down or
RP# is set to V
IL
. Upon initial device power-up and
after exit from deep power-down mode, the STS
pin defaults to RY/BY# operation where STS low
indicates that the WSM is busy. STS High Z
indicates that the WSM is ready for a new
operation.
To reconfigure the STS pin to other modes, the
STS Configuration is issued followed by the
appropriate configuration code. The three alternate
configurations are all pulse mode for use as a
system interrupt. The STS Configuration command
functions independently of the V
PP
voltage and
RP# must be V
IH
.
Table 11 STS Configuration Coding Description
CONFIGURATION
BITS
EFFECTS
00H
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at the
completion of Block Erase, Full Chip
Erase and Clear Block Lock-Bits
operations.
Set STS pin to pulsed output signal
for a specific write operation. In this
mode, STS provides low pulse at the
completion of (Multi) Byte Write and
Set Block Lock-Bit operation.
Set STS pin to pulsed output signal
for specific write and erase operation.
STS provides low pulse at the
completion of Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration operations.
01H
02H
03H
Table 12 Write Protection Alternatives
OPERATION
BLOCK
LOCK-BIT
0
WP#
EFFECT
Block Erase or
(Multi) Word/Byte
Write
V
IL
or V
IH
Block Erase and (Multi) Word/Byte Write Enabled
V
IL
Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled
V
IH
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled
V
IL
All unlocked blocks are erased, locked blocks are not erased
V
IH
All blocks are erased
V
IL
Set Block Lock-Bit Disabled
V
IH
Set Block Lock-Bit Enabled
V
IL
Clear Block Lock-Bits Disabled
V
IH
Clear Block Lock-Bits Enabled
1
Full Chip Erase
0, 1
X
Set Block Lock-Bit
X
Clear Block Lock-Bits
X
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PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
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| LH28F004SUB-Z9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| LH28F004SU-LC | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:4M (512K 】 8) Flash Memory |
| LH28F004SU-NC | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:4M (512K 】 8) Flash Memory |
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