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參數(shù)資料
| 型號： | LH155R |
| 英文描述： | Industrial Control IC |
| 中文描述： | 工業(yè)控制IC |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 288K |
| 代理商： | LH155R |
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16
LH155BA
2.4.3. ICON DISPLAY MODE
This mode enables 2 output pins for icon display
and this mode can display 1 icon.
Source are V
DD
and V
SS
. Since this mode is
independent of other mode completely, when using
this mode, lower power operation is possible.
Waveform of this mode is below.
To display, use internal clock or external clock.
When using external clock, input clock pulse to
EXA pin (120 Hz : Duty 50%).
When using icon display and segment display,
input 500 Hz, duty 50% pulse.
ICON
1
V
DD
V
DD
ICON
2
V
SS
V
SS
2.5. Display Starting Line Register
This register is for determining display starting line
(usually the most upper line) corresponding to
COM
0
when displaying the display data RAM.
The register is also used in picture-scrolling.
The 6-bit display starting address is set in this
register by display starting line setting command.
The register is preset every timing of FLM signal
variation in the display line counter. The line
counter counts up being synchronized with LP input
and generates line addresses which sequentially
read out 128-bit data from display RAM to LCD
drive circuit.
2.6. Addressing of Display RAM
Display RAM consists of 128 x 64 bits memory,
and enables access in 8-bit unit to an address
specified by X address and Y address from MPU.
It is possible to set up the addresses X and Y so
that they can increment automatically with the
address control register. The increment is made
every time display RAM is read or written from
MPU. (See
Section 4. "COMMAND FUNCTION"
.)
Though the X direction side is selected by X
address while the Y direction side by Y address,
10
H
-FF
H
in the X address are inhibited and do not
have the X address set in these addresses.
In the Y direction side, the 128-bit display data are
internally read into the display data latch circuit at
the rising of LP every one line cycle, and are output
from the display data latch circuit at the falling of LP.
43
H
-FF
H
in the Y address are inhibited and do not
have the Y address set in these addresses.
When FLM signals being output in one frame cycle
are at "H", the value in the display starting line
register are preset in the line counter and the line
counter counts up at the falling of LP signals.
The display line address counter is synchronized
with each timing signal of the LCD system to
operate and is independent of address counters X
and Y.
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PDF描述 |
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| LH155P | Industrial Control IC |
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| LH155L | Industrial Control IC |
| LH1554P | LCD Display Driver |
| LH1554M | LCD Display Driver |
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