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參數(shù)資料
| 型號(hào)： | LH155BA |
| 廠商： | Sharp Corporation |
| 英文描述： | 128-Segment and 64-Common Outputs LCD Driver IC with A Built-in RAM |
| 中文描述： | 128段和64共同的產(chǎn)出與液晶顯示驅(qū)動(dòng)芯片內(nèi)置的內(nèi)存， |
| 文件頁數(shù)： | 19/51頁 |
| 文件大小： | 288K |
| 代理商： | LH155BA |
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LH155BA
2.10. Display Timing Generator
The display timing generator generates a timing
clock necessary for internal operation and timing
pulses (LP, FLM, and M) by inputting the master
clock CK or by the oscillation circuit of OSCI and
OSCO.
By setting up master/slave mode (M/S), the state of
timing pulse pins and the timing generator changes.
2.11. Signal Generation to Display Line
Counter, and Display Data
Latching Circuit
Both the clock to the line counter and latching
signals to display data latching circuit from the
display clock (LP) are generated.
Synchronized with the display clock, the line
addresses of display RAM are generated and 128-
bit display data are latched to display-data latching
circuit to output to the LCD drive circuit (SEG
output).
Readout of the display data to the LCD drive circuit
is completely independent of MPU. Therefore, a
MPU that has no relationship the readout operation
of the display data can access it.
2.12. Generation of The Alternating
Signal (M) and The Synchronous
Signal (FLM)
LCD alternating signal (M) and synchronous signal
(FLM) are generated by the display clock (LP). The
FLM generates alternated drive waveform to the
LCD drive circuit. Normally, the FLM generates
alternated drive waveform every frame unit (M-
signal level is reversed every one frame).
But by setting up data (n – 1) in an n-line reverse
register and n-line alternating command (NLIN) at
"H", n-line reverse waveform is generated.
When the LH155BA is used in multi-chip, the
signals of LP, FLM, and M must be sent from
master side in the slave operation.
2.13. Display Data Latching Circuit
Display data latching circuit temporally latches
display data that is output display data to LCD drive
circuit from display RAM every one common period.
Normal display/reverse display, display ON/OFF,
and display all ON commands are operated by
controlling data in the latch. And no data within
display RAM changes.
M/S
PIN
MODE
LP
PIN
M
PIN
FLM
PIN
STATE OF TIMING
GENERATOR
Stop of LP, M, FLM
generation circuit
Operating state
L
Slave Input Input Input
H
Display Timing Pulse Pins and Timing Generator State
Master Output Output Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH155R | Industrial Control IC |
| LH155P | Industrial Control IC |
| LH155N | Industrial Control IC |
| LH155L | Industrial Control IC |
| LH1554P | LCD Display Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH155L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| LH155N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| LH155P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| LH155R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| LH1560 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
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