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參數(shù)資料
| 型號(hào)： | LG128643-FMDWH6V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LG128643-FMDWH6V |
| 中文描述： | LG128643 - FMDWH6V |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 136K |
| 代理商： | LG128643-FMDWH6V |
LG128643-FMDWH6V - 7 -
4. OPERATING PRINCIPLES & METHODES
4.1 I/O Buffer
Input buffer controls the status between the enable and display of chip. Unless the CS1 or
CS2 is in active mode, input or output of data and instruction does not execute. Therefore
internal state is not changed. But /RST can operates regardless CS1 or CS2.
4.2 Input Register
Input register is provided to interface with MPU that operates in different frequency. Input
register stores the data temporarily before writing it into display data RAM.
When CS1 or CS2 is in the active mode, R/W and RS select the input register. The data
from MPU is written into input register, then into display data RAM. Data is latched at
falling edge of the E signal and then written into the display data RAM automatically by
internal operation.
4.3 Output Register
Output register stores the data temporarily which is read from display data RAM when
CS1 or CS2 is in active mode and R/W and RS=H, stored data in display data RAM is
latched in output register. When CS1 or CS2 is in active mode and R/W=H, RS=L, status
data (busy check) can be read out.
To read the contents of display data RAM, twice access of read instruction is needed. In
first access, data in display data RAM is latched into output register. In second access,
MPU can read data that is latched in output register. That is, to read the data in display
data RAM, it needs dummy read. But status read does not need dummy read.
RS
R/W
L
Instruction
L
H
Status read (busy check)
L
Data write (from input register to display data RAM)
H
H
Data read (from display data RAM to output register)
4.4 Reset
The system can be initialized by setting /RST terminal at low level when turning power on,
receiving instruction from MPU. When /RST becomes low, following procedure is
occurred.
1. Display off
2. Display start line register is set by 0. (Z-address 0)
While /RST is low level, no instruction except status read can be accepted. Reset status
appears at DB4 of status byte, after DB4 becomes
“
L
”
, any instruction can be accepted.
Function
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