參數(shù)資料
型號(hào)： LFX500C-3F900C
廠商： Lattice Semiconductor Corporation
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:16-26 RoHS Compliant: No
中文描述： 在ispXPGA架構(gòu)
文件頁(yè)數(shù)： 33/89頁(yè)
文件大?。?/td> 941K
代理商： LFX500C-3F900C
Lattice Semiconductor
ispXPGA Family Data Sheet
33
LOCKIN Time
REFCLK and SS_CLKIN Timing
SERIALIZER Timing
1
Symbol
Description
Mode
Condition
Min.
Max.
Units
t
SCLOCK
CSPLL Lock Time
All
After Input is Stabilized
—
25
μ
S
t
RCP
t
RCP
t
RCP
t
RCP
t
RCP
t
RCP
t
RCP
t
CDRLOCK
CDRPLL Lock-in Time
SS
With SS mode Sync Pattern
—
1024
1
10B12B
With 10B12B Sync Pattern
—
1024
8B10B
With 8B10B Idle Pattern
—
480
t
SYNC
t
CAL
t
SUSYNC
t
HDSYNC
1. REFCLK clock period.
SyncPat Length
SS
1200
—
CAL Duration
SS
1100
—
SyncPat Set-up Time to CAL
SS
50
—
SyncPat Hold Time from CAL
SS
50
—
Symbol
Description
Mode
Condition
Min.
Max.
Units
f
DREFCLK
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on one link.
8B10B,
10B12B
-100
100
ppm
t
JPPREFCLK
t
PWREFCLK
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
All
40-250 (MHz)
-0.005
0.005
UIPP
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
All
1
—
ns
t
RFREFCLK
REFCLK, SS_CLKIN Rise/Fall Time. (20% to 80%
or 80% to 20%)
All
—
2
ns
Symbol
Description
Mode
Condition
Min.
Max.
Units
t
JPPSOUT
SOUT Peak-to-Peak Output Data Jitter
All
—
0.25
UIPP
t
JPP8B10B
SOUT Peak-to-Peak Random Jitter
8B10B
900 Mbps w/k28.7-
—
130
ps
SOUT Peak-to-Peak Deterministic Jitter
8B10B
900 Mbps w/k28.5+
—
110
ps
t
RFSOUT
SOUT Output Data Rise/Fall Time (20%,
80%)
LVDS
—
700
ps
BLVDS
—
900
ps
t
COSOUT
REFCLK to SOUT Delay
SS/8B10B
2Bt
2
+ 2
1Bt
2
+ 2
2Bt
2
+ 10
1Bt
2
+ 10
ns
10B12B
ns
t
SKTX
Skew of SOUT with Respect to
SS_CLKOUT
SS
—
250
ps
t
CKOSOUT
t
HSITXDDATAS
t
HSITXDDATAH
TXD Data Hold Time
1. The SIN and SOUT jitter speci
fi
cations listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYPASS mode.
2. Bt = bit time period. High speed serial bit time.
3. Internal timing for reference only.
SS_CLKOUT to bit0 of SOUT
SS
2Bt
2
+ t
SKTX
2Bt
2
+ t
SKTX
1.5
ns
TXD Data Setup Time
All
Note 3
—
ns
All
Note 3
—
1.0
ns
相關(guān)PDF資料
PDF描述
LFX1200C-3F900C Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:16-26 RoHS Compliant: No
LFX500C-3F900I Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:16-26 RoHS Compliant: No
LFX1200C-3F900I The ispXPGA architecture
LFX200C-4F900C Circular Connector; Body Material:Aluminum Alloy; Series:MS3112; No. of Contacts:8; Connector Shell Size:16; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Circular Contact Gender:Pin RoHS Compliant: No
LFX500C-4F900C PT 8C 8#16 SKT RECP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX500C-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:The ispXPGA architecture
LFX500C-3FE680C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500C-3FE680I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500C-3FH516C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX500C-3FH516I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
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