參數(shù)資料
型號: LFX200B-03FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 81/119頁
文件大?。?/td> 0K
描述: IC FPGA 200K GATES 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 2704
RAM 位總計: 113664
輸入/輸出數(shù): 160
門數(shù): 210000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
60
Signal Descriptions
1
Signal Name
Signal Type
Description
General Purpose
BKy_IOx
1,2
Input/Output
General purpose I/O number x in I/O Bank y
GCLK
n/In 7
Input
Global clock/input
8
GSR
Input
Global Set/Reset
NC
No Connect
GND
Ground
VCC
VCC
Core logic power supply
VCCJ
VCC
IEEE 1149.1 TAP power supply
VCCOy
2
VCC
I/O Bank y power supply
VREFy
2
Input
I/O Bank y reference voltage
DXN, DXP
Output
Temperature Sensing Diodes, provide a differential voltage, which
corresponds to the temperature of the device.
Test and Program/Configuration
TMS
Input
Test Mode Select
TCK
Input
Test Clock
TDI
Input
Test Data In
TDO
Output
Test Data Out
TOE
Input
Test Output Enable tri-states all I/O pins when driven low
CFG0
Input
Selects the SRAM memory configuration type (Peripheral or
E
2CMOS Refresh)
PROGRAMb
Input
Initiates download from E
2CMOS or the peripheral port to SRAM
memory (active low)
DONE
Bi-directional
Indicates when configuration is complete
INITb
Bi-directional
Indicates the device is ready for programming (active low)
READ
Input
Selects the READ operation when in sysCONFIG mode
CCLK
Input
sysCONFIG Configuration Clock
CSb
Input
sysCONFIG Chip Select (active low)
DATA[0:7]
Bi-directional
sysCONFIG Peripheral Port Data I/O
sysCLOCK PLL
3
PLL_FBKz
Input
Optional external feedback
PLL_RSTz
Input
Optional external M divider reset
CLK_OUTz
Internal Signal Clock output (routable to any I/O)
PLL_LOCKz
Internal Signal Lock output (routable to any I/O)
GNDP0
GND
Left side PLL Ground
GNDP1
GND
Right side PLL Ground
VCCP0
VCC
Left side PLL power supply
VCCP1
VCC
Right side PLL power supply
sysHSI Block
4, 5
HSImA_SINP, HSImB_SINP
Input
P-side of differential serial data input
HSImA_SINN, HSImB_SINN
Input
N-side of differential serial data input
HSImA_SOUTP, HSImB_SOUTP
Output
P-side of differential serial data output
HSImA_SOUTN, HSImB_SOUTN
Output
N-side of differential serial data output
HSImA_SYDT, HSImB_SYDT
Internal Signal Symbol alignment detect
HSImA_RECCLK, HSImB_RECCLK
Internal Signal Recovered clock
SELECT
DEVICES
DISCONTINUED
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