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參數(shù)資料
| 型號： | LFX1200C-3F900I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | The ispXPGA architecture |
| 中文描述： | 在ispXPGA架構 |
| 文件頁數(shù)： | 3/89頁 |
| 文件大?。?/td> | 941K |
| 代理商： | LFX1200C-3F900I |
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Lattice Semiconductor
ispXPGA Family Data Sheet
3
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and
fl
exibility allowing complex designs to be implemented quickly and ef
fi
ciently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be con
fi
gured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed,
fl
exible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of con
fi
gurable input and output buffers connected directly to the PICs. These buffers can
be con
fi
gured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices with-
out the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
相關PDF資料 |
PDF描述 |
|---|---|
| LFX200C-4F900C | Circular Connector; Body Material:Aluminum Alloy; Series:MS3112; No. of Contacts:8; Connector Shell Size:16; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Circular Contact Gender:Pin RoHS Compliant: No |
| LFX500C-4F900C | PT 8C 8#16 SKT RECP |
| LFX125B-3F900C | The ispXPGA architecture |
| LFX200B-3F900C | The ispXPGA architecture |
| LFX500B-3F900C | The ispXPGA architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LFX1200C-3FE680C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX1200C-3FE680I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX1200C-3FH516C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX1200C-3FH516I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX1200C-3FN256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
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