參數(shù)資料
型號(hào): LFM34INTPU1A
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 19/60頁(yè)
文件大?。?/td> 0K
描述: ADAPTER MPC5534 324-BGA
標(biāo)準(zhǔn)包裝: 1
模塊/板類(lèi)型: 適配器板
MPC5534 Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
26
Figure 4. Pad Output Delay
3.13
AC Timing
3.13.1
Reset and Configuration Pin Timing
3Fast
00
3.2
2.4
10
01
2.2
20
10
2.1
30
11
2.1
50
4
Pullup/down (3.6 V max)
7500
50
5
Pullup/down (5.5 V max)
9500
50
1 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
VDD = 1.35–1.65 V; VDDE = 3.0–3.6 V; VDDEH = 3.0–3.6 V; VDD33 and VDDSYN = 3.0–3.6 V; and TA = TL to TH.
2 This parameter is supplied for reference and guaranteed by design (not tested).
3 The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal.
4 The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.
5 This parameter is guaranteed by characterization rather than 100% tested.
Table 19. Reset and Configuration Pin Timing 1
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
RESET pulse width
tRPW
10
tCYC
2
RESET glitch detect pulse width
tGPW
2—
tCYC
Table 18. Derated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)
1 (continued)
Spec
Pad
SRC/DSC
(binary)
Out Delay 2, 3, 4
(ns)
Rise / Fall 3, 5
(ns)
Load Drive
(pF)
VDD 2
VOH
VOL
Rising-edge
out delay
Falling-edge
Pad
internal data
Pad
output
out delay
input signal
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