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參數(shù)資料
| 型號(hào)： | LFECP6E-5F900I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 63/117頁(yè) |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP6E-5F900I |
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www.latticesemi.com
4-1
Pinout Information_01.2
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During con
fi
guration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
con
fi
guration.
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
as assigned V
REF
inputs. When not used, they may be used as I/O pins.
10K ohm +/-1% resistor must be connected between this pad and ground.
GSRN
NC
GND
V
CC
I
—
—
—
V
CCAUX
—
V
CCIOx
—
V
REF1_x,
V
REF2_x
—
XRES
PLL and Clock Functions
(Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be con
fi
gured to be output.
Test and Programming
(Dedicated pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during con
fi
guration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
—
[LOC][num]_PLL[T, C]_IN_A
I
[LOC][num]_PLL[T, C]_FB_A
I
PCLK[T, C]_[n:0]_[3:0]
I
[LOC]DQS[num]
I
TMS
I
TCK
I
LatticeECP/EC Family Data Sheet
Pinout Information
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFECP6E-5T100C | Precision Chopper-Stabilized Operational Amplifier 14-PDIP |
| LFECP6E-5T100I | LatticeECP/EC Family Data Sheet |
| LFEC33E-3F256C | LatticeECP/EC Family Data Sheet |
| LFECP33E-3F256C | LatticeECP/EC Family Data Sheet |
| LFEC33E-3F256I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP6E-5FN256C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP6E-5FN256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP6E-5FN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 224 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP6E-5FN484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP6E-5FN672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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