參數(shù)資料
型號： LFECP6E-4F484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 768 CLBS, 6100 GATES, 420 MHz, PBGA484
封裝： 23 X 23 MM, FPBGA-484
文件頁數(shù)： 8/117頁
文件大小： 557K
代理商： LFECP6E-4F484I
2-5
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic Mode:
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
In this mode, the LUTs in each Slice are con
fi
gured as 4-input combinatorial lookup tables. A LUT4
Ripple Mode:
lowing functions can be implemented by each Slice:
Ripple mode allows the ef
fi
cient implementation of small arithmetic functions. In ripple mode, the fol-
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Ripple mode multiplier building block
Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode:
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information on using RAM
in LatticeECP/EC devices, please see details of additional technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
Logic
Ripple
RAM
SPR16x2
N/A
ROM
PFU Slice
PFF Slice
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
2-bit Arithmetic Unit
ROM16x1 x 2
ROM16x1 x 2
SPR16x2
1
DPR16x2
2
Number of slices
Note: SPR = Single Port RAM, DPR = Dual Port RAM
相關(guān)PDF資料
PDF描述
LFECP6E-4F672C Quad Low-Power Low-Voltage Operational Amplifier 14-PDIP
LFECP6E-4F672I LatticeECP/EC Family Data Sheet
LFECP6E-4F900I LatticeECP/EC Family Data Sheet
LFECP6E-4T100I LatticeECP/EC Family Data Sheet
LFECP6E-4T144C LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP6E-4F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-4F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-4F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-4F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-4FN256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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