- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377631 > LFECP40E-4F256C (Lattice Semiconductor Corporation) LinCMOS(TM) Dual Operational Amplifier 8-SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | LFECP40E-4F256C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LinCMOS(TM) Dual Operational Amplifier 8-SOIC |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊(cè) |
| 文件頁數(shù)： | 16/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP40E-4F256C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
2-13
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on speci
fi
c design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory con
fi
gurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1.
Normal
address) does not appear on the output.
– data on the output appears only during read cycle. During a write cycle, the data (at the current
2.
Write Through
– a copy of the input data appears at the output of the same port, during a write cycle.
3.
Read-Before-Write
– when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-16.
EBR
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
DO[35:0]
Single Port RAM
EBR
True Dual Port RAM
Pseudo-Dual Port RAM
ROM
AD[12:0]
CLK
CE
RST
DO[35:0]
CS[2:0]
EBR
EBR
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADW[12:0]
DI[35:0]
CLKW
CEW
WE
RST
CS[2:0]
ADR[12:0]
DO[35:0]
CER
CLKR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFECP40E-4F256I | LinCMOS(TM) Dual Operational Amplifier 8-SOIC |
| LFECP40E-4F484C | LatticeECP/EC Family Data Sheet |
| LFECP40E-4F484I | LatticeECP/EC Family Data Sheet |
| LFECP40E-4F672C | LinCMOS(TM) Dual Operational Amplifier 8-PDIP |
| LFECP40E-4F672I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP40E-4F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP40E-4F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP40E-4F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP40E-4F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP40E-4F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。