參數(shù)資料
型號： LFECP40E-3F484C
廠商： Lattice Semiconductor Corporation
英文描述： Dual uPower Low-Voltage Operational Amplifier 8-PDIP
中文描述： LatticeECP / EC的系列數(shù)據手冊
文件頁數(shù)： 31/117頁
文件大?。?/td> 557K
代理商： LFECP40E-3F484C
2-28
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIO Buffer
Each I/O is associated with a
fl
exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeECP/EC devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (V
CCIO
), and two voltage references V
REF1
and V
REF2
resources allow-
ing each bank to be completely independent from each other. Figure 2-33 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using V
CCIO.
LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as
fi
xed threshold
input independent of V
CCIO.
In addition to the bank V
CCIO
supplies, the LatticeECP/EC devices have a V
CC
core logic
power supply, and a V
CCAUX
supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be con
fi
gured to be a
reference voltage supply pin. Each I/O is individually con
fi
gurable based on the bank’s supply and reference volt-
ages.
相關PDF資料
PDF描述
LFECP40E-3F484I LatticeECP/EC Family Data Sheet
LFECP40E-3F672I LatticeECP/EC Family Data Sheet
LFECP40E-3F900I LatticeECP/EC Family Data Sheet
LFECP40E-3Q208I LatticeECP/EC Family Data Sheet
LFECP40E-3T100C LatticeECP/EC Family Data Sheet
相關代理商/技術參數(shù)
參數(shù)描述
LFECP40E-3F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP40E-3F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP40E-3F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP40E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP40E-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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