參數(shù)資料
型號： LFECP20E-3F484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA484
封裝： 23 X 23 MM, FPBGA-484
文件頁數(shù)： 34/117頁
文件大?。?/td> 557K
代理商： LFECP20E-3F484I
2-31
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-14. Supported Output Standards
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled to within speci
fi
ed limits, this allows for easy integration with the rest of the
system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Recommended Power Up Sequence
: As described in the previous paragraph, the supplies can be sequenced
in any order. However, once internal power good is achieved (determined by VCC, VCCAUX, VCCIO bank 5) the
part releases I/Os from tri-state and the management of I/Os becomes the designers responsibility. To simplify a
system design it is therefore recommended that supplies be sequenced VCCIO, VCC, VCCAUX.
Output Standard
Drive
V
CCIO
(Nom.)
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS
1
LVPECL
1
RSDS
1
1. Emulated with external resistors.
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
1.8
1.5
1.2
—
—
—
—
—
3.3
1.8
1.5
3.3
2.5
1.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
2.5
相關(guān)PDF資料
PDF描述
LFECP20E-3F672I LinCMOS(TM) Quad Operational Amplifier 14-SOIC
LFECP20E-3F900I LatticeECP/EC Family Data Sheet
LFECP20E-3T100C LinCMOS(TM) Quad Operational Amplifier 14-PDIP
LFECP20E-3T100I LinCMOS(TM) Quad Operational Amplifier 14-PDIP
LFECP40E-5T144C LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP20E-3F672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP20E-3F672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP20E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP20E-3FN256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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