參數(shù)資料
型號： LFECP10E-4FN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 93/163頁
文件大?。?/td> 0K
描述： IC FPGA 10.2KLUTS 484FPBGA
標準包裝： 60
系列： ECP
邏輯元件/單元數(shù)： 10200
RAM 位總計： 282624
輸入/輸出數(shù)： 288
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
2-32
Architecture
LatticeECP/EC Family Data Sheet
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP/EC devices contain two possible ports that can be used for device configuration. The test access
port (TAP), which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial
configuration.
The TAP supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Con-
figuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and
the rest being dual-use pins (please refer to TN1053 for more information about using the dual-use pins as general
purpose I/O). There are four configuration options for LatticeECP/EC devices:
1.
Industry standard SPI memories.
2.
Industry standard byte wide flash and ispMACH 4000 for control/addressing.
3.
Configuration from system microprocessor via the configuration bus or TAP.
4.
Industry standard FPGA board memory.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
configuration port is selected, that port is locked and another configuration port cannot be activated until the next
power-up sequence.
For more information about device configuration, please see the list of technical documentation at the end of this
data sheet.
Internal Logic Analyzer Capability (ispTRACY)
All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide
capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace
memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-
pile time.
For more information about ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
External Resistor
LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP10E-4FN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-4FN672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-4FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-4Q208C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs 147 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-4Q208I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs 147 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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