Figure 3-5. DDR Timings tDQVBS
參數(shù)資料
型號: LFECP10E-4FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 111/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 195I/O 256-BGA
標準包裝: 90
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計: 282624
輸入/輸出數(shù): 195
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應商設備封裝: 256-FPBGA(17x17)
3-15
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-5. DDR Timings
tDQVBS
Data Valid Before DQS
All
0.20
0.20
0.20
UI
tDQVAS
Data Valid After DQS
All
0.20
0.20
0.20
UI
fMAX_DDR
DDR Clock Frequency
All
95
200
95
166
95
133
MHz
Primary and Secondary Clock6
fMAX_PRI
2
Frequency for Primary Clock Tree
All
420
378
340
MHz
tW_PRI
Clock Pulse Width for Primary
Clock
All
1.19
1.19
1.19
ns
tSKEW_PRI
Primary Clock Skew within an I/O
Bank
All
250
300
350
ps
1. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF.
2. Using LVDS I/O standard.
3. DDR timing numbers based on SSTL I/O.
4. DDR specifications are characterized but not tested.
5. UI is average bit period.
6. Based on a single primary clock.
7. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
Timing v.G 0.30
LatticeECP/EC External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Device
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
tDQVAS
tDQVBS
DQ and DQS Write Timings
t
DQS
DQ
DQS
DQ
DVEDQ
tDVADQ
DQ and DQS Read Timings
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