Figure 2-27. Input Register DDR Waveforms Figure 2-28. INDDRXB Primitive Output Regist" />
參數(shù)資料
型號(hào): LFECP10E-3F256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 84/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 195I/O 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計(jì): 282624
輸入/輸出數(shù): 195
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
2-24
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-27. Input Register DDR Waveforms
Figure 2-28. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-29 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
AB
C
D
E
F
BD
DI
(In DDR Mode)
D0
D2
DQS
A
C
DQS
Delayed
IDDRXB
LSR
QA
D
ECLK
QB
DDRCLKPOL
SCLK
CE
相關(guān)PDF資料
PDF描述
LFXP10E-3F388C IC FPGA 9.7KLUTS 244I/O 388-BGA
LFXP10E-3FN388C IC FPGA 9.7KLUTS 388FPBGA
LFXP10C-3F388C IC FPGA 9.7KLUTS 244I/O 388-BGA
LT3083EDF#TRPBF IC REG LDO ADJ 3A 12-DFN
MIC5322-MGYMT TR IC REG LDO 2.8V/1.8V .15A 6TMLF
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP10E-3F484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-3F484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP10E-3F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-3F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet