參數(shù)資料
型號: LFEC40E-3T100I
廠商: Lattice Semiconductor Corporation
英文描述: LatticeECP/EC Family Data Sheet
中文描述: LatticeECP / EC的系列數(shù)據(jù)手冊
文件頁數(shù): 28/117頁
文件大小: 557K
代理商: LFEC40E-3T100I
2-25
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-28. Output Register Block
Figure 2-29. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-30 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the
fl
ip-
fl
ops that then feeds the output. The
fl
ip-
fl
op can be con
fi
gured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
D
Q
D
D-Type
/LATCH
Q
ONEG0
From
Routing
CLK1
Programmed
Control
DO
Latch
LE*
*Latch is transparent when input is low.
OPOS0
OUTDDN
0
1
0
1
To sysIO
Buffer
ODDRXB
LSR
Q
DB
CLK
DA
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