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參數(shù)資料
| 型號(hào)： | LFEC40E-3F672I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | FPGA, 5120 CLBS, PBGA672 |
| 封裝： | 27 X 27 MM, FPBGA-672 |
| 文件頁(yè)數(shù)： | 4/117頁(yè) |
| 文件大小： | 557K |
| 代理商： | LFEC40E-3F672I |
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www.latticesemi.com
2-1
Architecture_01.3
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
Architecture Overview
The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programma-
ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM
(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks as
shown in Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for
fl
exibility allowing complex designs to be implemented quickly and ef
fi
ciently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be con
fi
gured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be con
fi
gured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device con
fi
guration. The LatticeECP/EC devices use 1.2V as their core volt-
age.
LatticeECP/EC Family Data Sheet
Architecture
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC40E-3F900I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3Q208I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3T100C | LatticeECP/EC Family Data Sheet |
| LFEC40E-3T100I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3T144C | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC40E-3F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3Q208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3Q208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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