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參數(shù)資料
| 型號： | LFEC40E-3F256I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 24/117頁 |
| 文件大小： | 557K |
| 代理商： | LFEC40E-3F256I |
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2-21
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-23. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
Figure 2-23. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-24.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be con
fi
gured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-24 shows the assignment of DQS pins in each set of 16
PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
PIO B
PADA
"T"
PADB
"C"
OPOS0
ONEG0
OPOS1
ONEG1
TD
INCK
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
DQS
PIO A
sysIO
Buffer
DDRCLKPOL
IOLD0
IOLT0
D0
D1
DDRCLK
DI
IPOS1
IPOS0
INCK
INDD
INFF
D0
D1
DDRCLK
TD
Output
Register Block
(2 Flip Flops)
Tristate
Register Block
(2 Flip Flops)
Input
Register Block
(5 Flip Flops)
CLKO
CEO
LSR
GSR
CLKI
CEI
Control
Muxes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC40E-3F484C | LatticeECP/EC Family Data Sheet |
| LFEC40E-3F484I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3F672I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3F900I | LatticeECP/EC Family Data Sheet |
| LFEC40E-3Q208I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC40E-3F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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