參數(shù)資料
型號(hào): LFEC33E-3T144I
廠商: Lattice Semiconductor Corporation
英文描述: LatticeECP/EC Family Data Sheet
中文描述: LatticeECP / EC的系列數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù): 12/117頁(yè)
文件大?。?/td> 557K
代理商: LFEC33E-3T144I
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2-9
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from the CLKOP, from the clock net, or from an external pin. There is a PLL_LOCK sig-
nal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during con
fi
guration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
1
DCS
DCS
1. Smaller devices have fewer PLL related lines.
4 Secondary Clocks per Quadrant
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
Primary Clock
Secondary Clock
Routing
Clock to Slice
GND
4
3
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