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參數資料
| 型號： | LFEC20E-5F256C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | LatticeECP / EC的系列數據手冊 |
| 文件頁數： | 10/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC20E-5F256C |
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2-7
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and ef
fi
cient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
Clock Input
PLL Input
PLL Input
Clock Input
PLL Input
From Routing
Clock Input
From Routing
PLL
PLL
PLL
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Note: Smaller devices have two PLLs.
相關PDF資料 |
PDF描述 |
|---|---|
| LFEC20E-5F256I | LatticeECP/EC Family Data Sheet |
| LFEC33E-4F256C | ECONOLINE: RSZ/P - 1kVDC |
| LFEC33E-4F256I | LatticeECP/EC Family Data Sheet |
| LFEC33E-4F484C | LatticeECP/EC Family Data Sheet |
| LFEC33E-4F484I | LatticeECP/EC Family Data Sheet |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LFEC20E-5F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-5F484C | 功能描述:FPGA - 現場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-5F672C | 功能描述:FPGA - 現場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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