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| 型號(hào)： | LFEC20E-4F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, FPBGA-484 |
| 文件頁(yè)數(shù)： | 18/117頁(yè) |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC20E-4F484C |
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2-15
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-17. Comparison of General DSP and LatticeECP-DSP Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be con
fi
gured to support the following four elements:
MULT
MAC
MULTADD
MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
(Multiply)
(Multiply, Accumulate)
(Multiply, Addition/Subtraction)
The number of elements available in each block depends in the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. In addition by selecting ‘dynamic operation’ in the ‘Signed/
Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly by select-
ing ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction
on every cycle.
Width of Multiply
MULT
MAC
MULTADD
MULTADDSUM
x9
8
4
4
2
x18
4
2
2
1
x36
1
—
—
—
Multiplier 0
Operand
A
Operand
B
Operand
A
Operand
B
Operand
A
Operand
B
Multiplier 1
Multiplier
(k-1)
Accumulator
Output
m/k
loops
Single
Multiplier
x
x
x
x
Operand
A
Accumulator
Operand
B
M loops
Function implemented in
General purpose DSP
Function implemented
in LatticeECP
Σ
Σ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC20E-4F484I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4F672C | LatticeECP/EC Family Data Sheet |
| LFEC20E-4F672I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T100I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC20E-4F484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-4F672C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-4F672I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-4F900C | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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