參數(shù)資料
型號： LFEC20E-3F484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA484
封裝： 23 X 23 MM, FPBGA-484
文件頁數(shù)： 32/117頁
文件大?。?/td> 557K
代理商： LFEC20E-3F484C
2-29
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-33. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
con
fi
gured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamp.
2.
Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be con
fi
gured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers.
Supported Standards
The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually con
fi
gurable
V
REF1(2)
V
REF2(2)
GND
B
V
CCIO2
V
REF1(3)
V
REF2(3)
GND
B
V
CCIO3
V
REF1(7)
V
REF2(7)
GND
B
V
CCIO7
V
REF1(6)
V
REF2(6)
GND
Note: N and M are the maximum number of I/Os per bank.
B
V
CCIO6
V
R
G
Bank 5
V
C
V
R
V
R
G
Bank 4
V
C
V
R
V
R
G
Bank 0
V
C
V
R
V
R
G
Bank 1
V
C
V
R
M
相關(guān)PDF資料
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LFECP6E-3F672C LatticeECP/EC Family Data Sheet
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC20E-3F484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC20E-3F672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC20E-3F672CAU1 制造商:Lattice Semiconductor 功能描述:LFEC20E-3F672CAU1
LFEC20E-3F672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC20E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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