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    參數(shù)資料
    型號: LFEC1E-5F256I
    廠商: Lattice Semiconductor Corporation
    英文描述: LatticeECP/EC Family Data Sheet
    中文描述: LatticeECP / EC的系列數(shù)據(jù)手冊
    文件頁數(shù): 33/117頁
    文件大小: 557K
    代理商: LFEC1E-5F256I
    2-30
    Architecture
    Lattice Semiconductor
    LatticeECP/EC Family Data Sheet
    options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
    Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
    BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
    (together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
    tion on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical infor-
    mation at the end of this data sheet.
    Table 2-13. Supported Input Standards
    Input Standard
    V
    REF
    (Nom.)
    V
    CCIO
    1
    (Nom.)
    Single Ended Interfaces
    LVTTL
    LVCMOS33
    2
    LVCMOS25
    2
    LVCMOS18
    LVCMOS15
    LVCMOS12
    2
    PCI
    HSTL18 Class I, II
    HSTL18 Class III
    HSTL15 Class I
    HSTL15 Class III
    SSTL3 Class I, II
    SSTL2 Class I, II
    SSTL18 Class I
    Differential Interfaces
    Differential SSTL18 Class I
    Differential SSTL2 Class I, II
    Differential SSTL3 Class I, II
    Differential HSTL15 Class I, III
    Differential HSTL18 Class I, II, III
    LVDS, LVPECL, BLVDS, RSDS
    1. When not speci
    fi
    ed V
    CCIO
    can be set anywhere in the valid operating range.
    2. JTAG inputs do not have a
    fi
    xed threshold option and always follow V
    CCJ.
    0.9
    1.08
    0.75
    0.9
    1.5
    1.25
    0.9
    1.8
    1.5
    3.3
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