參數(shù)資料
型號(hào)： LFEC15E-5FN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 74/163頁
文件大?。?/td> 0K
描述： IC FPGA 10.2KLUTS 288I/O 484-BGA
標(biāo)準(zhǔn)包裝： 60
系列： EC
邏輯元件/單元數(shù)： 15400
RAM 位總計(jì)： 358400
輸入/輸出數(shù)： 352
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
其它名稱： 220-1232
2-15
Architecture
LatticeECP/EC Family Data Sheet
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the
parallel implementations.
Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be configured to support the following four elements:
MULT
(Multiply)
MAC
(Multiply, Accumulate)
MULTADD
(Multiply, Addition/Subtraction)
MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
Multiplier 0
Operand
A
Operand
B
Operand
A
Operand
B
Operand
A
Operand
B
Multiplier 1
Multiplier
(k-1)
Accumulator
Output
m/k
loops
Single
Multiplier
x
xx
x
Operand
A
Accumulator
Operand
B
M loops
Function implemented in
General purpose DSP
Function implemented
in LatticeECP
Σ
相關(guān)PDF資料
PDF描述
RBC10DREI-S13 CONN EDGECARD 20POS .100 EXTEND
VE-2TF-CW-F3 CONVERTER MOD DC/DC 72V 100W
GBC06DRXI CONN EDGECARD 12POS DIP .100 SLD
ATFC-0402-3N0-BT INDUCTOR THIN FILM 3.0NH 0402
ASM25DTMS-S189 CONN EDGECARD 50POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC15E-5FN484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC15E-5FN672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC15E-5FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC15E-5Q208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC15E-5Q208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*