參數(shù)資料
型號(hào): LFEC10E-5F256C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 3.3V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述: FPGA, 1280 CLBS, 10200 GATES, 420 MHz, PBGA256
封裝: 17 X 17 MM, FPBGA-256
文件頁(yè)數(shù): 2/117頁(yè)
文件大?。?/td> 557K
代理商: LFEC10E-5F256C
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www.latticesemi.com
1-1
Introduction_01.2
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
Features
Extensive Density and Package Options
1.5K to 41K LUT4s
65 to 576 I/Os
Density migration supported
sysDSP Block (LatticeECP Versions)
High performance multiply and accumulate
4 to 10 blocks
4 to 10 36x36 multipliers or
– 16 to 40 18x18 multipliers or
32 to 80 9x9 multipliers
Embedded and Distributed Memory
18 Kbits to 645 Kbits sysMEM Embedded
Block RAM (EBR)
Up to 163 Kbits distributed RAM
Flexible memory resources:
Distributed and block memory
Flexible I/O Buffer
Programmable sysIO buffer supports wide
range of interfaces:
Table 1-1. LatticeECP/EC Family Selection Guide
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
SSTL 3/2 Class I, II, SSTL18 Class I
HSTL 18 Class I, II, III, HSTL15 Class I, III
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
Implements interface up to DDR400 (200MHz)
sysCLOCK PLLs
Up to 4 analog PLLs per device
Clock multiply, divide and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY internal logic analyzer capability
SPI boot
fl
ash interface
1.2V power supply
Low Cost FPGA
Features optimized for mainstream applications
Low cost TQFP and PQFP packaging
Device
LFEC1
12
16
192
1.5
6
18
2
1.2
2
LFEC3
16
24
384
3.1
12
55
6
1.2
2
LFEC6/
LFECP6
24
32
768
6.1
25
92
10
4
16
1.2
2
LFEC10/
LFECP10
32
40
1280
10.2
41
277
30
5
20
1.2
4
LFEC15/
LFECP15
40
48
1920
15.4
61
350
38
6
24
1.2
4
LFEC20/
LFECP20
44
56
2464
19.7
79
424
46
7
28
1.2
4
LFEC33/
LFECP33
64
64
4096
32.8
131
535
58
8
32
1.2
4
LFEC40/
LFECP40
64
80
5120
41.0
164
645
70
10
40
1.2
4
PFU/PFF Rows
PFU/PFF Columns
PFUs/PFFs
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
V
CC
Voltage (V)
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1. LatticeECP devices only.
1
1
67
97
112
67
97
145
160
97
147
195
224
147
195
288
195
352
360
400
360
496
496
576
LatticeECP/EC Family Data Sheet
Introduction
相關(guān)PDF資料
PDF描述
LFEC10E-5F256I LatticeECP/EC Family Data Sheet
LFEC20E-3T144C LatticeECP/EC Family Data Sheet
LFEC20E-3T144I LatticeECP/EC Family Data Sheet
LFEC20E-4F256C LatticeECP/EC Family Data Sheet
LFEC20E-4F256I LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC10E-5F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC10E-5F484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10.2K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC10E-5F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC10E-5F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC10E-5F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet