- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4584 > LFEC10E-3QN208I (Lattice Semiconductor Corporation)IC FPGA 10.2KLUTS 208PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | LFEC10E-3QN208I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 98/163頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 10.2KLUTS 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | EC |
| 邏輯元件/單元數(shù)： | 10200 |
| RAM 位總計(jì)： | 282624 |
| 輸入/輸出數(shù)： | 147 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)當(dāng)前第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)
www.latticesemi.com
2-1
Architecture_02.0
September 2012
Data Sheet
2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Architecture Overview
The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/
O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as
shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core volt-
age.
LatticeECP/EC Family Data Sheet
Architecture
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LT1175IQ#TRPBF | IC REG LDO NEG ADJ .5A DDPAK-5 |
| LT3015IQ-5#TRPBF | IC REG LDO -5V 1.5A DDPAK-5 |
| LT3015IQ-3.3#TRPBF | IC REG LDO -3.3V 1.5A DDPAK-5 |
| IDT72V51236L7-5BBI | IC FLOW CTRL MULTI QUEUE 256-BGA |
| IDT72V51236L6BB | IC FLOW CTRL MULTI QUEUE 256-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC10E-3T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC10E-3T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC10E-3T144C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC10E-3T144I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC10E-3TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。