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參數(shù)資料
| 型號： | LF3304 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | Dual Line Buffer/FIFO |
| 中文描述： | 雙線路緩沖器/先進(jìn)先出 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 130K |
| 代理商： | LF3304 |
DEVICES INCORPORATED
Video Imaging Products
11
LF3304
Dual Line Buffer/FIFO
08/16/2000–LDS.3304-F
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed o protect the chip rom damaging
substrate injection currents and accu-
mulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to avoid
exposure to excessive electrical stress
values.
3. This device provides hard clamping
of transient undershoot. Input levels
below ground will be clamped begin-
ning at –0.6 V. The device can withstand
indefinite operation with inputs or out-
puts in the range of –0.5 V to +5.5 V.
Device operation will not be adversely
affected, however, input current levels
will be well in excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated
by:
NCV F
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with outputs changing every
cycle and no load, at a 40 MHz clock rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed but
not 100% tested.
9. AC specifications are tested with
NOTES
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of
I
OH
and
I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 μF ceramic capacitor should be
installed between
V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device
V
CC
and the tester common, and device
ground and tester common.
b. Ground and
V
CC
supply planes must
be brought directly to the DUT socket or
contactor fingers.
c. Input voltages on a test fixture should
be adjusted to compensate for inductive
ground and
V
CC
noise to maintain re-
quired DUT input levels relative to the
DUT ground pin.
10. Each parameter is shown as a mini-
mum or maximum value. Input require-
ments are specified from the point of view
of the external system driving the chip.
Setup time, for example, is specified as a
minimum since the external system must
supply at least that much time to meet the
worst-case requirements of all parts.
Responses from the internal circuitry are
specified from the point of view of the
device. Output delay, for example, is
specified as a maximum since worst-
case operation of any device always pro-
vides data within that time.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point with
datasheet loads. For the
t
DIS
test, the
transition is measured to the ±200mV
level from the measured steady-state
output voltage with ±10mA loads.
The balancing voltage, V
TH
, is set at
3.0 V for Z-to-0 and 0-to-Z tests, and
set at 0 V for Z-to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.0V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LF3304QC10 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:Dual Line Buffer/FIFO |
| LF3304QC12 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:Dual Line Buffer/FIFO |
| LF3304QC15 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:Dual Line Buffer/FIFO |
| LF-330A | 制造商:NEC 制造商全稱:NEC 功能描述:Noise Filters |
| LF-330K4 | 制造商:NEC 制造商全稱:NEC 功能描述:Noise Filters |
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