Philips Semiconductors Linear Products
Product specification
LF198/LF298/LF398
Sample-and-hold amplifiers
August 31, 1994
881
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in “sample” mode; V
S
=
±
15V; T
J
= 25
°
C; -11.5V3 V
IN
≤
+11.5V; C
H
=0.01
μ
F;
and R
L
= 10k
. Logic reference voltage = 0V and logic voltage = 2.5V.
SYMBOL
PARAMETER
TEST CONDITIONS
LF198/LF298
Min
Typ
LF398
Typ
2
UNIT
Max
3
5
25
75
Min
Max
7
10
50
100
V
OS
Input offset voltage
4
T
J
=25
°
C
1
mV
Full temperature range
T
J
=25
°
C
Full temperature range
T
J
=25
°
C
T
J
=25
°
C,
R
L
=10k
Full temperature range
I
BIAS
Input bias current
4
5
10
nA
Input impedance
10
10
0.002
10
10
0.004
Gain error
0.005
0.01
%
0.02
0.02
Feedthrough attenuation
ratio at 1kHz
T
J
=25
°
C,
C
h
=0.01
μ
F
86
96
80
90
dB
Output impedance
T
J
=25
°
C,
“HOLD“ mode
Full temperature range
T
J
=25
°
C, C
h
=0.01
μ
F, V
OUT
=0
T
J
≤
25
°
C
0.5
2
0.5
4
4
6
“HOLD“ step
2
Supply current
4
Logic and logic reference
input current
Leakage current into hold
capacitor
4
0.5
4.5
2.0
5.5
1.0
4.5
2.5
6.5
mV
mA
I
CC
T
J
= 25
°
C
2
10
2
10
μ
A
T
J
=25
°
C, “HOLD“ mode
30
100
30
200
pA
t
AC
Acquisition time to 0.1%
V
OUT
=10V, C
h
=1000pF
C
h
=0.01
μ
F
4
20
4
20
μ
s
Hold capacitor charging
current
Supply voltage rejection
ratio
Differential logic threshold
V
IN
-V
OUT
=2V
5
5
mA
V
OUT
=0
80
110
80
110
dB
T
J
=25
°
C
0.8
1.4
2.4
0.8
1.4
2.4
V
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in “sample“ mode, V
S
=
±
15V, T
J
=25
°
C, -11.5V
≤
V
IN
≤
+11.5V, C
h
= 0.01
μ
F,
and R
= 10k
. Logic reference voltage = 0V and logic voltage = 2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01
μ
F hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25
°
C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25
°
C value for each 11
°
C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. The parameters are guaranteed over a supply voltage of
±
5 to
±
18V.