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參數(shù)資料
| 型號： | LF2272 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | Colorspace Converter/Corrector (3 x 12-bits) |
| 中文描述： | 色彩空間轉換器/校正（3 × 12位） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 249K |
| 代理商： | LF2272 |
DEVICES INCORPORATED
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
08/16/2000–LDS.2272-I
3
Video Imaging Products
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers. All timing specifi-
cations are referenced to the rising
edge of CLK.
Inputs
A
11-0
, B
11-0
, C
11-0
— Data Inputs
A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multi-
plier input registers.
KA
9-0
, KB
9-0
, KC
9-0
— Coefficient Inputs
KA, KB, and KC are the 10-bit regis-
tered coefficient input ports. Data
presented to these ports is latched into
the corresponding internal coefficient
register set defined by CWEL
1-0
(Table 3) on the next rising edge of
CLK. Table 2 shows which coefficient
registers are available for each coeffi-
cient input port.
T
ABLE
2.
C
OEFFICIENT
I
NPUTS
INPUT PORT
REG. AVAILABLE
KA
KA1, KA2, KA3
KB
KB1, KB2, KB3
KC
KC1, KC2, KC3
CWEL
1
-
0
COEFFICIENT SET
00
Hold All Registers
01
KA1, KB1, KC1
10
KA2, KB2, KC2
11
KA3, KB3, KC3
T
ABLE
3.
C
OEFF
. R
EG
. U
PDATE
Outputs
X
11-0
, Y
11-0
, Z
11-0
— Data Outputs
X, Y, and Z are the 12-bit registered
data output ports.
Controls
CWEL
1-0
— Coefficient Write Enable
The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 3) on the next clock cycle.
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