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參數(shù)資料
| 型號： | LF2242QC33 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 12/16-bit Half-Band Interpolating/ Decimating Digital Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 136K |
| 代理商： | LF2242QC33 |
DEVICES INCORPORATED
LF2242
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
Video Imaging Products
2
08/16/2000–LDS.2242-K
Controls
INT — Interpolation Control
When INT is LOW and DEC is HIGH
(Table 1), the device internally forces
every other incoming data sample to
zero. This effectively halves the input
data rate and the output amplitude.
DEC — Decimation Control
When DEC is LOW and INT is HIGH
(Table 1), the output register is strobed on
every other rising edge of CLK (driven at
half the clock rate), decimating the output
data stream.
F
IGURE
1.
F
REQUENCY
R
ESPONSE
OF
F
ILTER
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all regis-
ters. All timing specifications are refer-
enced to the rising edge of CLK.
SYNC — Synchronization Control
Incoming data is synchronized by hold-
ing SYNC HIGH on CLK
N
, and then by
bringing SYNC LOW on CLK
N+1
with
the first word of input data. SYNC is held
LOW until resynchronization is desired,
or it can be toggled at half the clock rate.
For interpolation (INT = LOW), input
data should be presented at the first ris-
ing edge of CLK for which SYNC is LOW
and then at every alternate rising edge of
CLK thereafter. SYNC is inactive if DEC
and INT are equal (pass-through mode).
Inputs
SI
11–0
— Data Input
12-bit two’s complement data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is SI
0
(Figure 2).
Outputs
SO
15-0
Data Output
The current 16-bit result is available on
the SO
15-0
outputs. The LF2242’s limiter
ensures that a valid full-scale (7FFF
positive or 8000 negative) output will be
generated in the event of an internal
overflow. The LSB is SO
0
(Figure 2).
0
0.1
S
0.2
S
0.3
S
0.4
S
0.5
S
FREQUENCY (NORMALIZED)
0
–10
–20
–30
–40
–50
–60
–70
–80
G
INT
DEC
MODE
0
0
Pass-through*
0
1
Interpolate
1
0
Decimate
1
1
Pass-through*
*Input and output registers run at full
clock rate
T
ABLE
1.
M
ODE
S
ELECTION
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