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參數資料
| 型號： | LDR3325PT-R |
| 廠商： | 意法半導體 |
| 英文描述： | VERY LOW DROP DUAL VOLTAGE REGULATOR |
| 中文描述： | 極低降雙電壓調節(jié)器 |
| 文件頁數： | 2/13頁 |
| 文件大?。?/td> | 384K |
| 代理商： | LDR3325PT-R |
LDRxxyy
2/13
Table 1: Absolute Maximum Ratings
Absolute Maximum Rating are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Table 2: Thermal Data
Figure 2: Connection Diagram
(top view)
Table 3: Pin Description
Table 4: Order Codes
Symbol
Parameter
Value
Unit
V
I1
&
V
I2
INH
I
O
P
TOT
T
STG
T
A
DC Input Voltage
Shutdown Voltage
Output Current
Power Dissipation
Storage Temperature Range
Operating Ambient Temperature Range
-0.3 to 15
-0.3 to 15
Internally Limited
Internally Limited
-50 to +150
-40 to +125
V
V
°C
°C
Symbol
Parameter
PPAK
SPAK-7L
Unit
R
THJ-C
Junction to case thermal resistance
8
2
°C/W
Symbol
Pin N° for
PPAK
Pin N° for
SPAK-7L
Name and Function
GND
V
I1
V
I2
V
INH1
V
INH2
V
O1
V
O2
N.C.
3
2
1
4
2
1
3
5
6
7
Ground pin
Input 1 Supply Pin. Bypass with a 2.2μF capacitor to GND
Input 2 Supply Pin. Bypass with a 2.2μF capacitor to GND
Enable 1 Pin. Internally connected to V
I1
in the PPAK version
Enable 2 Pin. Internally connected to V
I2
in the PPAK version
Output 1 Pin. Bypass with a 4.7μF capacitor to GND Port
Output 2 Pin. Bypass with a 4.7μF capacitor to GND Port
Not Internally Connected
4
5
V
O1
V
O2
TYPE
PART NUMBERS
SPAK-7L
PPAK
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
2.5 V
3.3 V
1.8 V
3.3 V
1.8 V
2.5 V
LDR1825
LDR1833
LDR2518
LDR2533
LDR3318
LDR3325
LDR1825K7-R
LDR1833K7-R
LDR2518K7-R
LDR2533K7-R
LDR3318K7-R
LDR3325K7-R
LDR1825PT-R
LDR1833PT-R
LDR2518PT-R
LDR2533PT-R
LDR3318PT-R
LDR3325PT-R
SPAK-7L
PPAK
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