參數(shù)資料
型號: LD3985XX50
英文描述: ULTRA LOW DROP LOW NOISE BICMOS VOLTAGE REGULATORS LOW ESR CAPACITORS COMPATIBLE
中文描述: 超低壓差低噪聲BICMOS工藝電壓調(diào)節(jié)器兼容低ESR電容
文件頁數(shù): 2/12頁
文件大?。?/td> 439K
代理商: LD3985XX50
LD3985 SERIES
2/12
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) The input pin is able to withstand non repetitive spike of 6.5V for 200ms.
THERMAL DATA
CONNECTION DIAGRAM
(top view for SOT, top through view for Flip-Chip)
PIN DESCRIPTION
Symbol
Parameter
Value
Unit
V
I
V
O
V
INH
I
O
P
D
T
STG
T
OP
DC Input Voltage
DC Output Voltage
INHIBIT Input Voltage
Output Current
Power Dissipation
Storage Temperature Range
Operating Junction Temperature Range
-0.3 to 6 (*)
-0.3 to V
I
+0.3
-0.3 to V
I
+0.3
Internally limited
Internally limited
-65 to 150
-40 to 125
V
V
V
°C
°C
Symbol
Parameter
SOT23-5L
Flip-Chip
Unit
R
thj-case
R
thj-amb
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
81
255
°C/W
°C/W
170
Pin N°
SOT23-5L
Pin N°
Flip-Chip
Symbol
Name and Function
1
2
3
4
2
1
V
I
Input Voltage of the LDO
Common Ground
Inhibit Input Voltage: ON MODE when V
INH
1.2V, OFF MODE when V
INH
0.4V (Do not leave floating, not internally pulled down/up)
Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise
voltage
Output Voltage of the LDO
GND
V
INH
4
5
BYPASS
5
3
V
O
SOT23-5L
Flip-Chip
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