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參數(shù)資料
| 型號： | LCX024AKB |
| 廠商： | Sony Corporation |
| 英文描述： | 1.4cm (0.55-inch) NTSC/PAL Color LCD Panel |
| 中文描述： | 一點四厘米（0.55英寸）的NTSC / PAL彩色液晶面板 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 212K |
| 代理商： | LCX024AKB |
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LCX024AK
2. LCD Panel Operations
A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the
gate lines from the top to bottom of the panel.
The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by
controlling the enable and VCK pin. The enable pin should be High when not in use.
A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits
applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period.
Scanning direction of horizontal shift register can be switched with RGT pin. Scanning direction is left to right
for RGT pin at High level; and right to left for RGT pin at Low level. (These scanning directions are from a
front view.) Normally, set to High level.
Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to
apply a video signal to the dot. The same procedures lead to the entire 218
×
521 dots to display a picture in
a single vertical scanning period.
Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted
against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal
synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is
required to apply video signal to the panel.
The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the V
DD
potential of gate output inverter drops to approximately 8.5V. This
pin shall be grounded when not in use.
The video signal shall be input with polarity-inverted system in every horizontal cycle.
Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle
are shown below:
Vertical display cycle 218H (13.84ms)
1
2
218
217
(1) Vertical display cycle
VD
VST
VCK
Horizontal display cycle (47.3μs)
1
2
3
4
5
175
174
(2) Horizontal display cycle (right scan)
HD
HST
HCK1
HCK2
HST is sampled at first for HCK1.
The horizontal display cycle consists of 521/3 = 174 clock pulses because of RGB simultaneous sampling.
Refer to Description of Operation "3. RGB Simultaneous Sampling."
VST is sampled at first for VCK.
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| LCX026ALE | 2.3cm (0.9-inch) Black-and-White LCD Panel |
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| LCX026 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:2.3cm (0.9-inch) Black-and-White LCD Panel |
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| LCX026ALE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:2.3cm (0.9-inch) Black-and-White LCD Panel |
| LCX026ALF | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:2.3cm (0.9-inch) Black-and-White LCD Panel |
| LCX026ALG | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:2.3cm (0.9-inch) Black-and-White LCD Panel |
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