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參數(shù)資料
| 型號： | lCM7217BlJl |
| 廠商： | Intersil Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Digit LED Display, Programmable Up/Down Counter |
| 中文描述： | 4位LED顯示，可編程加/減計數(shù)器 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 137K |
| 代理商： | LCM7217BLJL |
9-18
Detailed Description
Control Outputs
The CARRY/BORROW output is a positive going pulse
occurring typically 500ns after the positive going edge of the
COUNT INPUT. It occurs when the counter is clocked from
9999 to 0000 when counting up and from 0000 to 9999 when
counting down. This output allows direct cascading of
counters. The CARRY/BORROW output is not valid during
load counter and reset operation. When the count is 6000 or
higher, a reset generates a CARRY/BORROW pulse.
The EQUAL output assumes a negative level when the
contents of the counter and register are equal.
The ZERO output assumes a negative level when the
content of the counter is 0000.
The CARRY/BORROW, EQUAL and ZERO outputs will drive
a single TTL load over the full range of supply voltage and
ambient temperature; for a logic zero, these outputs will sink
1.6mA at 0.4V and for a logic one, the outputs will source
>60
μ
A. A 10k
pull-up resistor to V
DD
on the EQUAL or
ZERO outputs is recommended for highest speed operation,
and on the CARRY/BORROW output when it is being used
for cascading. Figure 2 shows control outputs timing
diagram.
Display Outputs and Control
The Digit and SEGment drivers provide a decoded
7-segment display system, capable of directly driving com-
mon anode LED displays at typical peak currents of
35mA/seg. This corresponds to average currents of
8mA/seg at 25% multiplex duty cycle. For the common cath-
ode versions, peak segment currents are 12.5mA, corre-
sponding to average segment currents of 3.1mA. Figure 1
shows the multiplex timing. The DISPLAY pin controls the
display output using three level logic. The pin is self-biased
to a voltage approximately
1
/
2
(V
DD
); this corresponds to
normal operation. When this pin is connected to V
DD
, the
segments are disabled and when connected to V
SS
, the
leading zero blanking feature is inhibited. For normal opera-
tion (display on with leading zero blanking) the pin should be
left open. The display may be controlled with a 3 position
SPDT switch; see Test Circuit.
Multiplex SCAN Oscillator
The on-board multiplex scan oscillator has a nominal free-
running frequency of 2.5kHz. This may be reduced by the
addition of a single capacitor between the SCAN pin and the
positive supply. Capacitor values and corresponding nominal
oscillator frequencies, digit repetition rates, and loading
times are shown in Table 1.
FIGURE 10A.
FIGURE 10B.
FIGURE 10C.
FIGURE 10. BRIGHTNESS CONTROL CIRCUITS
R2
20k
1M
0.01
μ
F
C
SCAN INPUT
ICM7217
R1
10k
1M
0.01
μ
F
SCAN INPUT
ICM7217
500
500
3k
0.05
μ
F
SCAN INPUT
ICM7217
10k
200
0.05
μ
F
7
4
8
3
2
6
1
8s
ICM7555
0V
V
DD
= 5V
ICM7217
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