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參數(shù)資料
| 型號(hào)： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | LCK4950 |
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Data Sheet
November 2001
LCK4950
Low-Voltage PLL Clock Driver
Features
I
Fully integrated phase-locked loop (PLL)
I
Oscillator or crystal reference input
I
Output frequency up to 180 MHz
I
Outputs disable in high impedance
I
Compatible with
PowerPC
,
Intel
, and high-
performance RISC microprocessors
I
TQFP packaging
I
Output frequency configurable
I
±35 ps typical cycle-to-cycle jitter
I
Pin compatible with the
Motorola
MPC950 clock
driver
Description
The LCK4950 is a PLL-based clock driver device
intended for high-performance clock tree designs.
The LCK4950 is 3.3 V compatible with output
frequencies of up to 180 MHz and output skews of
200 ps. The LCK4950 can accommodate the most
demanding tree designs by employing a fully
differential PLL design. This minimizes cycle-to-cycle
jitter, which is critical when the device is acting as the
reference clock for PLLs in today
’
s microprocessors
and ASICs. The device has nine low-skew
configurable outputs for support of the clocking
needs of the various high-performance
microprocessors.
To provide input reference clock flexibility, two
selectable division ratios are available on the
LCK4950. The internal V
CO
runs at either 2x or 4x
the high-speed output. The FBSEL pin is used to
select between a divide by 8 or a divide by 16 of the
V
CO
frequency to be compared with the input
reference. These selections allow the input reference
to be either one-half, one-fourth, or one-eighth of the
high-speed output.
The LCK4950 is capable of scan clock distribution or
system diagnostics due to an external test clock
input. The REF_SEL pin allows the selection
between a crystal input to an on-chip oscillator for the
reference or selection of a TTL level oscillator input
directly. Only a parallel resonant crystal is required
for the onboard crystal oscillator external
components.
The LCK4950 is fully 3.3 V compatible and requires
no external loop filter components. All inputs accept
LVCMOS or LVTTL compatible levels while the
outputs provide LVCMOS levels with the capability to
drive terminated 50
transmission lines. The
LCK4950 can drive two traces, giving the device an
effective fan out of 1:18 for series-terminated 50
lines. For optimum performance and board density,
the device is packaged in a 7 mm x 7 mm 32-lead
TQFP package.
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