參數(shù)資料
型號: LC89977M
廠商: Sanyo Electric Co.,Ltd.
英文描述: CCD Delay Line for PAL(用于PAL電視機(jī)系統(tǒng)的CCD延遲線)
中文描述: 防治荒漠化公約延遲線(用于PAL制式電視機(jī)系統(tǒng)的防治荒漠化公約延遲線對于PAL)
文件頁數(shù): 3/7頁
文件大?。?/td> 83K
代理商: LC89977M
No. 5545-3/7
LC89977M
CONT
Mode (representative)
Chrominance signal delay (number of CCD stages)
Luminance signal delay (number of CCD stages)
Low
PAL/GBI
2H (1703.5) + 0H (1)
1H (848)
High
4.43NTSC
1H (845.5) + 0H (1)
1H (842)
Control Pin Functions
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Switching voltage level: low
V
L
V
H
–0.3
0.0
+0.5
V
Switching voltage level: high
2.0
5.0
6.0
V
Switching Voltage Levels
Function of the 3FSC Pin
This pin provides a 3fsc clock signal generated by the 3
×
PLL frequency multiplier circuit.
Note:
*
Since the control pins have built-in pull-down resistors (about 70 k
), leaving these pins opens effectively sets them to the low level.
Continued on next page.
Parameter
Symbol
Switch states
Ratings
Unit
SW1
SW2
SW3
Test conditions
min
typ
max
I
DD-1
I
DD-2
a
a
b
*
1
Supply current
b
a
b
*
1
27
32
37
mA
[Chrominance signal characteristics] (with no input to Y-IN)
V
INC-1
V
INC-2
V
OUTC-1
V
OUTC-2
G
VC-1
G
VC-2
C
D-1
C
D-2
L
NC-1
L
NC-2
L
CK3C-1
L
CK3C-2
L
CK1C-1
L
CK1C-2
N
C-1
N
C-2
Z
OC-1
Z
OC-2
T
DC-1
T
DC-2
a
a
b
*
2
DC output voltage
b
a
b
*
2
1.9
2.4
2.9
V
a
a
b
*
2
b
a
b
*
2
1.4
1.9
2.4
V
a
a
b
*
3
Voltage gain
b
a
b
*
3
–2
0
+2
dB
a
a
b
*
4
Comb depth
b
a
b
*
4
–40
–35
dB
a
a
b
*
5
Linearity
b
a
b
*
5
–0.3
0.0
+0.3
dB
a
a
b
*
6
Clock leakage (3fsc)
b
a
b
*
6
10
50
mVrms
a
a
b
*
6
Clock leakage (fsc)
b
a
b
*
6
0.5
1.5
mVrms
a
a
b
*
7
Noise
b
a
b
*
7
0.5
2.0
mVrms
a
a
a, b
*
8
Output impedance
b
a
a, b
*
8
200
350
500
a
a
b
*
9
0-H delay time
b
a
b
*
9
130
ns
Electrical Characteristics
at V
DD
= 5.0 V, Ta = 25°C, F
CLK
= 4.43361875 MHz, V
CLK
= 500 mVp-p
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