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參數(shù)資料
| 型號： | LC89962M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | NTSC Format Delay Line |
| 中文描述： | NTSC格式延遲線 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 98K |
| 代理商： | LC89962M |
Allowable Operating Ranges
at Ta = 25°C
Note 1. The input signal must be input with low impedance for correct operation of sync-tip clamping.
Electrical Characteristics
at Ta = 25°C, V
DD
= 5.0 V, CLK = 3.579545 MHz; 300 mV p-p
Test Conditions
1. The supply current with no input signal
2. The following formula is used to calculate the voltage gain (G
V
).
V
[mVp-p]
500 [mVp-p]
G
V
= 20log ——————— [dB]
3. The following formula is used to calculate the frequency characteristics (Gf).
V2 [mVp-p]
V1 [mVp-p]
G
f
= 20log —————— [dB]
During this test, adjust Vbias so that the input signal DC level is 250 mV higher than the clamp level.
No. 5420-2/6
LC89962, LC89962M
Parameter
Symbol
Switch states
min
typ
max
Unit
SW1
SW2
SW3
Test conditions
Supply current
I
DD
G
V
G
f
DG
a
a
a
*
1
5
15
25
mA
Voltage gain
a
b
a
*
2
–2
0
+2
dB
Frequency characteristics
b
b
a
*
3
–2
–1
0
dB
Differential gain
a
a
a
*
4
0
5
%
Differential phase
DP
a
a
a
*
4
0
5
deg
Linearity
LS
a
a
a
*
5
37
40
43
%
Clock leakage
Lck
a
b
a
*
6
5
50
mVrms
Noise
N
O
Z
O
TD
a
b
a
*
7
1
2
mVrms
μs
Output impedance
a
b
a
b
a
*
8
220
370
520
Delay time
a
b
*
9
63.33
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
V
CLK
F
CLK
V
IN
4.75
5.0
5.25
V
Clock input amplitude
Sine wave
200
300
500
mVp–p
Clock frequency
3.579545
MHz
Signal input amplitude
(
*
1)
500
572
mVp–p
Output signal symbol
Input signal
V
OUT
Sine wave: 200 kHz, 500 mV p-p
Output signal symbol
Input signal
V1
Sine wave: 200 kHz, 200 mV p-p
V2
Sine wave: 3.58 MHz, 200 mV p-p
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| LC89971 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Multi-system CCD Delay Line |
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| LC89972 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PAL CCD Delay Line |
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