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參數(shù)資料
| 型號： | LC898093KW |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | LC898093KW |
3. EFM Clock Generation Block Pins
FR
(input)
EFM reproduction PLL VCO bias resistor connection.
PDO, PDS1, PDS2, PDS3
(output)
EFM reproduction PLL lag-lead filter connection.
PCKISTF
(input)
EFM reproduction PLL frequency comparator charge pump bias resistor connection.
PCKISTP
(input)
EFM reproduction PLL phase comparator charge pump bias resistor connection.
RPO
(output)
P/N balance adjustment.
OPP
(input)
P/N balance adjustment.
PCK2
(output)
EFM reproduction bit clock output.
4. Jitter Discrimination Pins
JITC
(output)
Jitter output.
5. Spindle Speed Detection Pins
FG
(input)
Input for the speed monitor signal from the spindle driver.
6. Audio Interface Pins
LOUT, ROUT
(output)
Left and right channel audio signal outputs.
7. RF Amplifier Interface Pins
LDON
(output)
RF amplifier interface.
8. Write Strategy Pins
WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT
(I/O)
Write strategy signal connections.
9. ATIP Decoder Related Pins
ATIPSYNC
(output)
ATIP synchronization detection signal. (For monitoring)
BIDATA, BICLK
(I/O)
Input mode: Input of the biphase data and biphase clock when an external ATIP demodulator is used.
Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For
monitoring)
WOBBLE
(input)
Wobble signal is input when the internal ATIP demodulator is used.
ACRCNG
(output)
Outputs the result of the ATIP decoder CRC check. (For monitoring)
No. 6614-11/12
LC898023K
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