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參數(shù)資料
| 型號： | LC898023KW |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | LC898023KW |
PS No. 6614-12/12
LC898023K
<Other Pins>
RESET
(input)
The LC898023K reset input. A low level input resets the LC898023K.
This pin must be held low for at least 1 μs when power is first applied.
TEST4 to TEST0
(input)
Test inputs. These pins must be connected to ground.
XTALCK0
(input),
XTAL0
(output)
Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder
and decoder blocks, including the DRAM interface.
XTALCK1
(input),
XTAL1
(output)
Main clock for the SCSI block. The LC898023K is designed so that it can operate even when the ECC and SCSI
blocks are not synchronized. Providing a 20 MHz input to the XTALCK0 and XTALCK1 pins assures that correct,
synchronized transfer at 10 Mbyte/s (20 Mbyte/s for Ultra SCSI) can be achieved. The maximum frequency that can
be used is 20 MHz.
Since both edges of the clock signal are used by Ultra SCSI, the duty ratio must be correct. Add feedback resistors on
the XTALCK1 and XTAL1 pins and take other measures as required.
R, VCNT, PDO, R1, VCNT1, PD1, MDC1
(I/O)
Clock reproduction PLL circuit pins.
SUBSYNC
(output)
Subcode SYNC output signal from the CIRC encoder during recording. (For monitoring)
EFMG
(output)
Outputs a high level during recording.
SHOCK
(output)
Outputs a high level when a mechanical shock is detected.
LOCK
(output)
Outputs a high level when the PLL circuit is locked.
DEF
(input)
Inputs the defect detection signal.
HFL
(input)
Inputs the mirror detection signal.
This catalog provides information as of August, 2000. Specifications and information herein are subject to
change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
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