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參數(shù)資料
| 型號(hào)： | LC895297 |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP176 |
| 封裝： | SQFP-176 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大小： | 212K |
| 代理商： | LC895297 |
No. 5785-3/9
LC895297
[INOUT]
(1) D0 to D7, IO0 to IO15
(3) DD0 to DD15, ZDASP, ZPDIAG
(10) IOP0 to IOP7
(15) DRESP, DREQ
Note: XTAL, XTALCK, R0, VCNT0, PDO0, R1, VCNT1, PO11, PO21, BSN1, R2, VCNT2, PO12, PO22, and BSN2
The above pins are not covered by the electrical characteristics.
The 1-bit D/A converter block pins are only measured using a logic tester; no analog measurements are performed.
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
VIH
Micro-signal amplifier. Applicable pins: EFMI
3.2
V
Input low-level voltage
VIL
1.8
V
Output high-level voltage
VOH
IOH = –4 mA. Applicable pins:
VDD – 2.1
V
EFMO and ZEFMO
Output low-level voltage
VOL
IOL = 4 mA. Applicable pins:
0.4
V
EFMO and ZEFMO
Input leakage current
IIL
VI = VSS, VDD: Applicable pins: EFMI
–10
+10
μA
Output leakage current
IOZ
In high-impedance mode: Applicable pins:
–10
+10
μA
EFMO and ZEFMO
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V
EFM Input and Output Signals
External Clock Generator PLL Circuit
Figure 1 PLL Circuit
While the circuit structure is fixed, the values of the components will vary with the circuit board capacitance and other application circuit parameters.
Symbol
Currently used value
Notes
R1
7.5 kΩ
VCO adjustment resistor
R2
10 kΩ
Low-pass filter resistor
R3
200 Ω
Low-pass filter phase compensation resistor
C1
0.1 μF
Low-pass filter capacitor
C2
0.1 μF
VCO bias stabilization capacitor
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