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參數(shù)資料
| 型號： | LC89086M |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 64K |
| 代理商： | LC89086M |
The analog signal (AIN) is acquired on the falling edge of the clock input (CLK). The acquired analog signal is
converted to a digital code and is output from the digital outputs (D8 to D1, OF) on the clock falling edge delayed three
clock cycles from the clock cycle in which the analog signal was acquired.
No. 5428-3/6
LC89086M
Timing Chart
TWH
TWL
TAP
Td
1.5 V
N
N + 1
N + 2
N + 3
N – 4
N – 3
N –2
N – 1
N
Clock input
(CLK)
Analog input
(AIN)
Digital output
(D8 to D1,OF)
TOE
High impedance
1.5V
Output enable input
(OEB)
Digital output
(D8 to D1,OF)
TOD
A09018
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Resolution
Res
8
bit
Maximum conversion rate
Fs
20
MSPS
Linearity error
LE
DC accuracy
±1.0
LSB
Differential linearity error
DLE
DC accuracy
±1.0
LSB
Offset voltage
Voffset
DC accuracy
10
50
90
mV
Power dissipation
Pd
Fs = 20 MSPS
150
220
mW
Electrical AC Characteristics 2
at Ta = 25
°C, AV
DD = DVDD = 5 V, AVSS = DVSS = 0 V, VrefH = 2 V, VrefL = 0 V
Note: Test circuits must conform to the sample application circuit.
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