參數(shù)資料
型號: LC89052T
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO24
封裝: 0.225 INCH, TSSOP-24
文件頁數(shù): 3/42頁
文件大?。?/td> 482K
代理商: LC89052T
LC89052T
No.7457-11/42
8.3 Clocks
8.3.1 PLL (LPF)
The LC89052T incorporates a VCO (Voltage Controlled Oscillator) that can synchronize with sampling frequencies
of 30kHz to 195kHz.
The locking frequency is selected with PLLCK[1:0]. The VCO circuit can be stopped with PLLOPR.
The range of input data that can be received differs depending on the settings of PLLCK[1:0].
The (512/2)fs for the PLLCK[1:0] = "11" in the table below is the state where the PLL itself is synchronized with the
512fs clock, but the clock signal output from the CKOUT pin is 1/2 of the PLL locked frequency, which is 256fs.
See the chapter on the of output clock for further information.
We recommend the 256fs setting with PLLCK[1:0] = "00" for the systems such as portable equipment that need to
restrain the consumption electric power. We also recommend the 512fs setting with PLLCK[1:0] = "10" or the
(512/2)fs with PLLCK[1:0] = "11" for the systems such as AV amplifiers that require improved performance.
Table 8.3 Input Data Reception Ranges and PLL Lock Frequency Settings
PLLCK1
PLLCK0
PLL lock frequency
Input data reception range
0
256fs
30k to 195kHz
0
1
384fs
30k to 108kHz
1
0
512fs
30k to 108kHz
1
(512/2)fs
30k to 108kHz
LPF is the PLL loop filter connection pin. Use the correct recommended resistance and capacitance as values listed in
the table below according to the PLLCK[1:0] settings.
PLLCK1
PLLCK0
R0
C0
C1
0
1
150
0.047
F
0.0068
F
1
0
1
150
0.068
F
0.0047
F
Figure 8.2 PLL Loop Filter Configuration
LPF
R0
C0
C1
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