參數(shù)資料
型號(hào)： LC8901Q
廠商： Sanyo Electric Co.,Ltd.
英文描述： Digital Audio Interface Receiver
中文描述： 數(shù)字音頻接口接收器
文件頁(yè)數(shù)： 4/15頁(yè)
文件大小： 177K
代理商： LC8901Q
Pin Functions
LC8901 (DIP42S)
Note: The DIP42S package version has one fewer each of the digital system power supply and digital system ground pins than the QIP44M package version.
No. 4079-4/15
LC8901, 8901Q
Pin No.
Symbol
I/O
Pin function and circuit operation
1
DIN1
I
2
DIN2
I
Data input pins with built-in amplifiers
3
DIN3
I
4
DIN4
I
5
DGND
—
Digital system ground
6
DIN5
I
Data input pins without built-in amplifiers
7
DIN6
I
8
DOUT1
O
Input data through output
9
DOUT2
O
10
RC1
I
RC oscillator connection
11
RC2
O
12
LPF
I
High: LPF time constant switching mode, low: fixed mode. This pin is normally high.
13
STOP
I
High: VCO operation stopped, low: normal operation
14
TEST1
I
Test pins (These pins are normally low.)
15
TEST2
I
16
AV
DD
R
—
Analog system power supply
17
I
VCO oscillator band adjustment
18
AGND
—
Analog system ground
19
VIN
I
VCO free-running oscillator setup
20
VCO
O
PLL low-pass filter
21
DGND
—
Digital system ground
22
CLK
I
Clock mode switching. High: 512fs, low: 384fs
23
XSYS
I
Crystal mode setting. High: crystal mode
24
XIN1
I
Crystal oscillator connection
25
XIN2
O
26
DV
DD
LOCK
—
Digital system power supply
27
O
High: PLL locked, low: unlocked
28
ERROR
O
Error mute signal output
29
FS256
O
256fs clock output
30
CLKOUT
O
VCO oscillator and crystal oscillator clock output
31
EMPHA
O
High: emphasis present, low: no emphasis
32
BCLK
O
Bit clock output
33
DATAOUT
O
Audio data output
34
LRCK
O
Left/right clock output. High: left channel, low: right channel
35
SUB1
O
Sampling frequency output
36
SUB2
O
37
DO
O
Microprocessor interface output
38
DI
I
Microprocessor interface input
39
CE
I
Microprocessor interface chip enable input
40
CL
I
Microprocessor interface clock input
41
XMODE
I
Used to start system operation after power on.
42
DV
DD
—
Digital system power supply
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